1. Field of Invention
The present invention relates to semiconductor field, especially to semiconductor devices and manufacturing methods thereof, and more particularly, to a method of forming a dual contact plug for replacement gate and a semiconductor device manufactured by means of the method.
2. Description of Prior Art
With the increasingly smaller size of semiconductor device, inter-layer contacts and contact plugs (CA) must become smaller, and distances therebetween also become shorter and shorter. Fabricating increasingly smaller contacts and contact plugs by using conventional processes presents a number of problems. (1) As an etching depth on gate is different from that in source/drain regions, shorts may likely occur between a contact plug and the gate. (2) As an etching depth in the source/drain regions is large whereas a size of openings thereof is small (i.e., it has a small width/height ratio), a number of process defects such as underetch, cavities in metal-filling plugs, and so on may be caused. Thus, the selection of processes is restricted, and the parasitic resistance increases.
Hereunder, by referring to FIG. 1, the problems in the conventional processes will be described in details. FIG. 1 is a schematic diagram of a semiconductor device manufactured according to the conventional process. As shown in FIG. 1, the semiconductor device manufactured according to the conventional process mainly comprises: a Si substrate 100, an Inter-Layer Dielectric (ILD) layer 180, silicide regions 110, a metal gate 120, source/drain contact plugs 140, and a gate contact plug 130. The metal gate 120 is formed on a high-k dielectric layer 170 which is deposited on the Si substrate 100. A spacer 160 is formed to surround the high-k dielectric layer 170 and the metal gate 120. The inter-layer dielectric layer 180 is deposited on the Si substrate 100. The silicide regions 110 is formed on and embedded in the Si substrate 100. The source/drain contact plugs 140 and the gate contact plug 130 are formed in the inter-layer dielectric layer 180, in which the source/drain contact plugs 140 are in contact with the silicide regions 110 respectively and the gate contact plug 130 is in contact with the metal gate 120. Each of the source/drain contact plugs 140 and the gate contact plug 130 includes a liner 125 and conductive metal filled therein. As illustrated in FIG. 1, the etching depth Hca_gate of the etching process for forming the gate contact plug 130 is different from the etching depth Hca_sd of the etching process for forming the source/drain contact plugs 140; the source/drain contact plugs 140 have a smaller width/height ratio, so in forming the source/drain contact plugs 140, the number of process defects such as underetch, cavities in metal-filling plugs, and so on may exist therein more likely. Moreover, since the etching process for the source/drain contact plugs 140 has much stricter requirements, shorts between the source/drain contact plugs 140 and the metal gate 120 (denoted by the dashed line in FIG. 1) may be resulted in with a greater possibility.